MOUNTAIN VIEW, Calif., Feb. 3, 2015 /PRNewswire/ --
Highlights:
Synopsys, Inc. (Nasdaq: SNPS), a global leader providing software, IP and services used to accelerate innovation in chips and electronic systems, today announced that its collaboration with ARM to bring the power of 10X throughput of IC Compiler™ II place and route solution is enabling superior implementation of high-frequency, power-efficient designs by delivering a Reference Implementation flow for the newly announced ARM Cortex-A72 processor. The combination of industry-leading RTL synthesis and place-and-route solutions with a Reference Implementation flow optimized for the new CPU is already enabling engineers to deliver advanced designs for the next-generation of mobile devices.
"We have collaborated with Synopsys to ensure our mutual customers can bring innovative products to market quickly while meeting their performance, power and area targets," said Noel Hurley, general manager, CPU Group, ARM. "Our collaboration to create an optimized Reference Implementation with Synopsys IC Compiler II for the ARM Cortex-A72 processor will help designers take advantage of the latest technology to efficiently create products that deliver a premium mobile experience."
Reference Implementation for Cortex-A72 with Design Compiler Graphical and IC Compiler II
Based on the results of previous collaborations, including Reference Implementations for ARM Cortex-A57 and Cortex-A53 processors, the Reference Implementation for the Cortex-A72 core takes advantage of ARM POP IP in 16nm FinFET Plus process, Synopsys HPC methodology and the latest tools and features in the Galaxy Design Platform. To achieve up to 2.5 GHz performance in a mobile computing power envelope, the Reference Implementation includes support for Synopsys' Design Compiler Graphical tool for RTL synthesis, IC Compiler and IC Compiler II for place and route, and PrimeTime® solution for signoff and physical ECO. In addition, the Reference Implementation is compatible with the Lynx Design System. Synopsys technology key to achieving this performance and power level includes: physical guidance for a predictable implementation flow, concurrent clock and data optimization for a boost in frequency, advanced clock gating, low-power clock tree synthesis and multi-bit register optimization for dynamic power savings, and signoff leakage recovery for further power reduction.
IC Compiler II is Synopsys' latest offering in place-and-route and is a full-featured, production-ready netlist-to-GDSII implementation system delivering the highest throughput and productivity along with the best quality of results. Developed from the ground up to deliver a leap forward in productivity, IC Compiler II is built on a new, highly efficient, multi-everything infrastructure and offers ultra-high capacity design planning, unique new clock-building technology and advanced global analytical closure techniques. These technologies enable IC Compiler II to deliver a 5X speed-up in implementation runtime along with half the iterations required to achieve target performance, together providing a 10X boost in throughput.
"This collaboration with ARM brings the power of our new place-and-route solution to new Cortex-A72 processor based designs," said Antun Domic, executive vice president and general manager of the Design Group at Synopsys. "We have collaborated with ARM for more than 20 years to ensure that our mutual customers have the best tools and the methodology to implement their bold visions and advance the state-of-the-art of semiconductor designs."
Design solutions for new ARM suite of IP for premium mobile experience
Early adopters of ARM's new suite of IP for a premium mobile experience, which includes the ARM Cortex-A72 processor, CoreLink CCI-500 interconnect, Mali-T880 GPU, Mali-V550 video processor and Mali-DP500 display processor, have been successfully using Synopsys tools and methodology to design and verify their initial designs. Building on previous collaborations to enable ARMv8-A based processor and advanced Mali GPU designs as well as the new Reference Implementation for the Cortex-A72 core, Synopsys and ARM are collaborating to extend these solutions across the new IP suite to include: optimized implementation with the Galaxy Design Platform, including IC Compiler II; virtual prototyping with Virtualizer™ Development Kits (VDKs) for ARM v8-A based cores; optimized simulation, formal verification, advanced debug, verification methodology, as well as the next-generation verification IP, Verification Compiler™ product and ZeBu® solution for emulation; HAPS® FPGA-based prototyping systems; and a full chip design environment with the Lynx Design System. In addition, Synopsys Core Optimization Services have extensive experience helping designers optimize their CPU and GPU cores for performance, power and area.
For more information:
ARM and Synopsys will co-present results of their collaboration to create the Reference Implementation for the new ARM Cortex-A72 processor at the Synopsys Users Group Silicon Valley event, which will be held March 23-25, 2015, in Santa Clara. For more information and to register for the event, please go to http://www.synopsys.com/SNUG.
For more information about the ARM-Synopsys collaboration and Synopsys' optimized solutions for ARM Powered products, please navigate to http://www.synopsys.com/ARM.
About Synopsys
Synopsys, Inc. (Nasdaq:SNPS) accelerates innovation in the global electronics market. As a leader in electronic design automation (EDA) and semiconductor IP, Synopsys delivers software, IP and services to help engineers address their design, verification, system and manufacturing challenges. Since 1986, engineers around the world have been using Synopsys technology to design and create billions of chips and systems. Learn more at http://www.synopsys.com.
Safe Harbor Statement
This press release contains forward-looking statements within the meaning of Section 27A of the United States Securities Act of 1933 and Section 21E of the United States Securities Exchange Act of 1934, including statements regarding the expected outcome and benefits of the collaboration between Synopsys and ARM, including expected customer results with ARM and Synopsys solutions. These statements are based on current expectations and beliefs. Actual results could differ materially from those described by these statements due to risks and uncertainties including, but not limited to, technical or other difficulties in developing solutions, market acceptance of these solutions, unforeseen production or delivery delays, failure to perform as expected, product errors or defects and other risks as identified in the companies' respective filings with the U.S. Securities and Exchange Commission, including those described in the "Risk Factors" section of Synopsys' latest Quarterly Report on Form 10-Q.
Editorial Contacts:
Sheryl Gulizia
Synopsys, Inc.
650-584-8635
sgulizia@synopsys.com
Lisa Gillette-Martin
MCA, Inc.
650-968-8900 ext. 115
lgmartin@mcapr.com
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SOURCE Synopsys, Inc.
